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Michael Shoniker

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2010 – 2019

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2018
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Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn, Jie Han, Manish Rana, Witold Pedrycz:
Automatic Selection of Process Corner Simulations for Faster Design Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1312-1316 (2018)
2015
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Michael Shoniker, Bruce F. Cockburn, Jie Han, Witold Pedrycz:
Minimizing the number of process corner simulations during design verification. DATE 2015: 289-292

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