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Xiang Tian 0001
Person information
- affiliation: University of Edinburgh, School of Engineering, Institute of Integrated Systems, UK
Other persons with the same name
- Xiang Tian — disambiguation page
- Xiang Tian 0002 — Zhejiang University, Institute of Advanced Digital Technology and Instrumentation, Hangzhou, China
- Xiang Tian 0003 — South China University of Technology, School of Electronic and Information Engineering, Guangzhou, China
- Xiang Tian 0004 — Jiangsu University, School of Automotive and Traffic Engineering, Zhenjiang, China
- Xiang Tian 0005 — Qilu University of Technology (Shandong Academy of Sciences), School of Computer Science and Technology, Jinan, China (and 1 more)
- Xiang Tian 0006 — Shandong Normal University, Business School, Jinan, China
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2010 – 2019
- 2012
- [j4]Khaled Benkrid, Ali Akoglu, Cheng Ling, Yang Song, Ying Liu, Xiang Tian:
High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP. Int. J. Reconfigurable Comput. 2012: 752910:1-752910:15 (2012) - [j3]Xiang Tian, Khaled Benkrid:
Implementation of the Longstaff and Schwartz American Option Pricing Model on FPGA. J. Signal Process. Syst. 67(1): 79-91 (2012) - 2010
- [j2]Xiang Tian, Khaled Benkrid:
High-Performance Quasi-Monte Carlo Financial Simulation: FPGA vs. GPP vs. GPU. ACM Trans. Reconfigurable Technol. Syst. 3(4): 26:1-26:22 (2010) - [c4]Xiang Tian, Khaled Benkrid:
Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations. ReConFig 2010: 202-207
2000 – 2009
- 2009
- [c3]Xiang Tian, Khaled Benkrid:
Mersenne Twister Random Number Generation on FPGA, CPU and GPU. AHS 2009: 460-464 - 2008
- [j1]Xiang Tian, Khaled Benkrid, Xiaochen Gu:
High Performance Monte-Carlo Based Option Pricing on FPGAs. Eng. Lett. 16(3): 434-442 (2008) - [c2]Xiang Tian, Khaled Benkrid:
Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputer. FPT 2008: 81-88 - [c1]Xiang Tian, Khaled Benkrid:
Massively Parallelized Quasi-Monte Carlo financial Simulation on a FPGA Supercomputer. HPRCTA@SC 2008: 1-8
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