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Journal Articles
- 2020
[j4]Ahmed Ben Atitallah
, Manel Kammoun, Karim M. A. Ali, Rabie Ben Atitallah:
An FPGA comparative study of high-level and low-level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules. Int. J. Circuit Theory Appl. 48(8): 1274-1290 (2020)- 2019
- [j3]Karim M. A. Ali, Rabie Ben Atitallah, Abdessamad Ait El Cadi, Nizar Fakhfakh, Jean-Luc Dekeyser:
ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. Int. J. Reconfigurable Comput. 2019: 4298013:1-4298013:19 (2019) - [j2]Manel Kammoun, Ahmed Ben Atitallah, Karim M. A. Ali, Rabie Ben Atitallah:
Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks. J. Electronic Imaging 28(3): 033010 (2019) - 2018
- [j1]Mokhtar Bouain, Karim M. A. Ali, Denis Berdjag, Nizar Fakhfakh, Rabie Ben Atitallah:
An Embedded Multi-Sensor Data Fusion Design for Vehicle Perception Tasks. J. Commun. 13(1): 8-14 (2018)
Conference and Workshop Papers
- 2020
- [c6]Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, Smaïl Niar:
Cross-layer CNN Approximations for Hardware Implementation. ARC 2020: 151-165 - 2017
- [c5]Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser:
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. ARC 2017: 168-176 - [c4]Rabie Ben Atitallah, Karim M. A. Ali:
FPGA-Centric High Performance Embedded Computing: Challenges and Trends. DSD 2017: 390-395 - [c3]Yomna Ben Jmaa, Karim M. A. Ali, David Duvivier, Maher Ben Jemaa, Rabie Ben Atitallah:
An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis. HPCS 2017: 580-587 - 2015
- [c2]Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser:
Using hardware parallelism for reducing power consumption in video streaming applications. ReCoSoC 2015: 1-7 - 2014
- [c1]Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser:
A generic pixel distribution architecture for parallel video processing. ReConFig 2014: 1-8
Coauthor Index
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