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ORCIDBharath Narasimha Swamy
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2010 – 2019
- 2018
[j2]Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy
, André Seznec:
DITVA: Dynamic Inter-Thread Vectorization Architecture. J. Parallel Distributed Comput. 120: 267-281 (2018)- 2016
- [c5]Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec:
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP. SBAC-PAD 2016: 18-25 - 2015
- [b1]Bharath Narasimha Swamy:
Exploiting heterogeneous manycores on sequential code. (Utilisation de manycores hétérogènes sur du code séquentiel). University of Rennes 1, France, 2015 - [j1]Arjun Suresh, Bharath Narasimha Swamy, Erven Rohou, André Seznec:
Intercepting Functions for Memoization: A Case Study Using Transcendental Functions. ACM Trans. Archit. Code Optim. 12(2): 18:18:1-18:18:23 (2015) - [c4]Surya Narayanan, Bharath Narasimha Swamy, André Seznec:
An empirical high level performance model for future many-cores. Conf. Computing Frontiers 2015: 1:1-1:8 - [c3]Erven Rohou, Bharath Narasimha Swamy, André Seznec:
Branch prediction and the performance of interpreters: don't trust folklore. CGO 2015: 103-114 - 2014
- [c2]Surya Narayanan, Bharath Narasimha Swamy, André Seznec:
Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era. SBAC-PAD (Workshops) 2014: 36-41 - [c1]Bharath Narasimha Swamy, Alain Ketterlin, André Seznec:
Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores. SBAC-PAD 2014: 214-221
Coauthor Index
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