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2020 – today
- 2023
[c7]Raphaële Milan
, Loïc Lagadec, Théotime Bollengier, Lilian Bossuet, Ciprian Teodorov:
Secured-by-design systems-on-chip: a MBSE Approach. RSP 2023: 07:1-07:7- 2021
- [c6]Théotime Bollengier, Loïc Lagadec, Ciprian Teodorov:
Prototyping FPGA through overlays. RSP 2021: 15-21
2010 – 2019
- 2018
- [b1]Théotime Bollengier:
Du Prototypage à l'Exploitation d'Overlays FPGA. (From prototyping to exploitation of FPGA overlays). Université Bretagne-Loire, France 2018, 2018 - [c5]Jean-Christophe Le Lann, Théotime Bollengier, Mohamad Najem, Loïc Lagadec:
An Integrated Toolchain for Overlay-centric System-on-chip. ReCoSoC 2018: 1-8 - 2017
- [j1]Mohamad Najem, Théotime Bollengier, Jean-Christophe Le Lann, Loïc Lagadec:
Extended overlay architectures for heterogeneous FPGA cluster management. J. Syst. Archit. 78: 1-14 (2017) - [c4]Théotime Bollengier, Loïc Lagadec, Mohamad Najem, Jean-Christophe Le Lann, Pierre Guilloux:
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach. ARC 2017: 93-105 - 2016
- [c3]Théotime Bollengier, Mohamad Najem, Jean-Christophe Le Lann, Loïc Lagadec:
Demo: Overlay architectures for heterogeneous FPGA cluster management. DASIP 2016: 239-240 - 2014
- [c2]Loïc Lagadec, Jean-Christophe Le Lann, Théotime Bollengier:
A prototyping platform for virtual reconfigurable units. ReCoSoC 2014: 1-7 - 2012
- [c1]Adam Quotb, Jean-Baptiste Floderer, Théotime Bollengier, Rémi Fabre, Sylvie Renaud, Yannick Bornat:
Live demonstration: Real-time wavelet spike detection with in-vitro biological signals. BioCAS 2012: 79
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