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ORCIDQian Ge 0001
Person information
- affiliation (PhD 2019): University of New South Wales, Sydney, Australia
Other persons with the same name
- Qian Ge — disambiguation page
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2010 – 2019
- 2019
[b1]Qian Ge:
Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection. University of New South Wales, Sydney, Australia, 2019- [c5]Qian Ge, Yuval Yarom
, Tom Chothia, Gernot Heiser:
Time Protection: The Missing OS Abstraction. EuroSys 2019: 1:1-1:17 - 2018
- [j1]Qian Ge, Yuval Yarom, David A. Cock, Gernot Heiser:
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware. J. Cryptogr. Eng. 8(1): 1-27 (2018) - [c4]Qian Ge, Yuval Yarom, Gernot Heiser:
No Security Without Time Protection: We Need a New Hardware-Software Contract. APSys 2018: 1:1-1:9 - [i4]Qian Ge, Yuval Yarom, Tom Chothia, Gernot Heiser:
Time Protection: the Missing OS Abstraction. CoRR abs/1810.05345 (2018) - 2016
- [c3]Fangfei Liu, Qian Ge, Yuval Yarom, Frank McKeen, Carlos V. Rozas, Gernot Heiser, Ruby B. Lee:
CATalyst: Defeating last-level cache side channel attacks in cloud computing. HPCA 2016: 406-418 - [i3]Qian Ge, Yuval Yarom, Gernot Heiser:
Do Hardware Cache Flushing Operations Actually Meet Our Expectations? CoRR abs/1612.04474 (2016) - [i2]Qian Ge, Yuval Yarom, David A. Cock, Gernot Heiser:
A Survey of Microarchitectural Timing Attacks and Countermeasures on Contemporary Hardware. IACR Cryptol. ePrint Arch. 2016: 613 (2016) - 2015
- [c2]Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, Ruby B. Lee:
Last-Level Cache Side-Channel Attacks are Practical. IEEE Symposium on Security and Privacy 2015: 605-622 - [i1]Yuval Yarom, Qian Ge, Fangfei Liu, Ruby B. Lee, Gernot Heiser:
Mapping the Intel Last-Level Cache. IACR Cryptol. ePrint Arch. 2015: 905 (2015) - 2014
- [c1]David A. Cock, Qian Ge, Toby C. Murray, Gernot Heiser:
The Last Mile: An Empirical Study of Timing Channels on seL4. CCS 2014: 570-581
Coauthor Index
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