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ORCIDSadegh Yazdanshenas
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2020 – today
- 2020
[j10]Mohamed Eldafrawy
, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz:
FPGA Logic Block Architectures for Efficient Deep Learning Inference. ACM Trans. Reconfigurable Technol. Syst. 13(3): 12:1-12:34 (2020)
2010 – 2019
- 2019
- [j9]Sadegh Yazdanshenas, Vaughn Betz:
COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures. ACM Trans. Reconfigurable Technol. Syst. 12(1): 3:1-3:27 (2019) - [j8]Sadegh Yazdanshenas, Vaughn Betz:
The Costs of Confidentiality in Virtualized FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2272-2283 (2019) - [c7]Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz:
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. FPGA 2019: 94-103 - 2018
- [j7]Sadegh Yazdanshenas, Vaughn Betz:
Interconnect Solutions for Virtualized Field-Programmable Gate Arrays. IEEE Access 6: 10497-10507 (2018) - [j6]Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz:
Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 6:1-6:22 (2018) - [j5]Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz:
You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. ACM Trans. Reconfigurable Technol. Syst. 11(3): 20:1-20:23 (2018) - [c6]Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz:
Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. FPL 2018: 35-42 - [c5]Sadegh Yazdanshenas, Vaughn Betz:
Improving Confidentiality in Virtualized FPGAs. FPT 2018: 258-261 - 2017
- [c4]Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz:
Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. FPGA 2017: 115-124 - [c3]Sadegh Yazdanshenas, Vaughn Betz:
Quantifying and mitigating the costs of FPGA virtualization. FPL 2017: 1-7 - [c2]Sadegh Yazdanshenas, Vaughn Betz:
Automatic circuit design and modelling for heterogeneous FPGAs. FPT 2017: 9-16 - 2016
- [j4]Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi:
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3489-3498 (2016) - [c1]Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz:
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. FPT 2016: 4-11 - 2015
- [j3]Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi:
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1868-1878 (2015) - 2014
- [j2]Sadegh Yazdanshenas, Marzieh Ranjbar Pirbasti, Mahdi Fazeli, Ahmad Patooghy:
Coding Last Level STT-RAM Cache for High Endurance and Low Power. IEEE Comput. Archit. Lett. 13(2): 73-76 (2014) - [j1]Sadegh Yazdanshenas, Hossein Asadi:
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. IEEE Trans. Circuits Syst. II Express Briefs 61-II(10): 798-802 (2014)
Coauthor Index
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