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ORCIDAndreas Emeretlis
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- affiliation: University of Patras, Greece
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Journal Articles
- 2018
[j2]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
, Nikos S. Voros:
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. ACM Trans. Design Autom. Electr. Syst. 23(2): 26:1-26:24 (2018)- 2016
- [j1]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros:
A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. ACM Trans. Embed. Comput. Syst. 15(1): 19:1-19:28 (2016)
Conference and Workshop Papers
- 2022
- [c9]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros:
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. VLSI-SoC 2022: 1-6 - 2017
- [c8]Andreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros:
Task graph mapping and scheduling on heterogeneous architectures under communication constraints. SAMOS 2017: 239-244 - 2016
- [c7]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros:
A hybrid approach for mapping and scheduling on heterogeneous multicore systems. SAMOS 2016: 360-365 - 2015
- [c6]Andreas Emeretlis, V. Kefelouras, George Theodoridis, Maki Nanou, Christina Tanya Politi, Kristina Georgoulakis, George-Othon Glentis:
FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. EUSIPCO 2015: 1581-1585 - [c5]Maki Nanou, Andreas Emeretlis, Christina Tanya Politi, George Theodoridis, Kristina Georgoulakis, George-Othon Glentis:
40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. ICTON 2015: 1-4 - [c4]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros:
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. ISVLSI 2015: 119-124 - 2014
- [c3]Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros:
A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. IPDPS Workshops 2014: 176-182 - [c2]Andreas Emeretlis, George Theodoridis:
FPGA Implementations for Volterra DFEs. Panhellenic Conference on Informatics 2014: 23:1-23:5 - [c1]Andreas Emeretlis, George Theodoridis, George-Othon Glentis:
High-performance FPGA implementations of volterra DFEs for optical fiber systems. ReConFig 2014: 1-8
Coauthor Index
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