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2020 – today
- 2024
[j7]Yu Qian
, Xuegong Zhou, Hao Zhou, Lingli Wang:
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis. ACM Trans. Design Autom. Electr. Syst. 29(2): 25:1-25:33 (2024)- [i1]Zhen Li, Kaixiang Zhu, Xuegong Zhou, Lingli Wang:
An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learning. CoRR abs/2403.17395 (2024) - 2023
- [j6]Kaichuang Shi, Xuegong Zhou, Hao Zhou, Lingli Wang:
An Optimized GIB Routing Architecture with Bent Wires for FPGA. ACM Trans. Reconfigurable Technol. Syst. 16(1): 2:1-2:28 (2023) - [c32]Moucheng Yang, Kaixiang Zhu, Lingli Wang, Xuegong Zhou:
DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions. ICFPT 2023: 278-279 - [c31]Zhen Li, Hao Zhou, Lingli Wang, Xuegong Zhou:
AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization. ICFPT 2023: 294-295 - 2022
- [c30]Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang:
Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration. FPT 2022: 1-6 - 2021
- [j5]Siyu Xiong, Guoqing Wu, Xitian Fan, Xuan Feng, Zhongcheng Huang, Wei Cao, Xuegong Zhou, Shijin Ding, Jinhua Yu, Lingli Wang, Zhifeng Shi:
MRI-based brain tumor segmentation using FPGA-accelerated neural network. BMC Bioinform. 22(1): 421 (2021) - [c29]Su Zheng, Kaisen Zhang, Yaoguang Tian, Wenbo Yin, Lingli Wang, Xuegong Zhou:
FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays. FPT 2021: 1-10 - 2020
- [j4]Xuegong Zhou, Lingli Wang, Alan Mishchenko:
Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm. IEEE Trans. Computers 69(9): 1293-1307 (2020) - [c28]Yue Li, Wei Cao, Xuegong Zhou, Lingli Wang:
A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications. FPT 2020: 35-38 - [c27]Kaichuang Shi, Hao Zhou, Xuegong Zhou, Lingli Wang:
GIB: A Novel Unidirectional Interconnection Architecture for FPGA. FPT 2020: 174-181
2010 – 2019
- 2019
- [j3]Junqi Yuan, Jialing Chen, Lingli Wang, Xuegong Zhou, Yinshui Xia, Jianping Hu:
ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2330-2342 (2019) - [j2]Xuegong Zhou, Lingli Wang, Alan Mishchenko:
Fast Adjustable NPN Classification Using Generalized Symmetries. ACM Trans. Reconfigurable Technol. Syst. 12(2): 7:1-7:16 (2019) - [c26]Moucheng Yang, Tao Chen, Xuegong Zhou, Liang Zhao, Yunping Zhu, Lingli Wang:
A Complete CPU-FPGA Architecture for Protein Identification with Tandem Mass Spectrometry. FPT 2019: 295-298 - 2018
- [c25]Xuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko:
Fast Adjustable NPN Classification using Generalized Symmetries. FPL 2018: 1-7 - 2017
- [c24]Yipeng Yuan, Zhihua Feng, Xuegong Zhou:
An on-line debug method for FPGAs. ASICON 2017: 484-487 - [c23]Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang:
Accelerating low bit-width convolutional neural networks with embedded FPGA. FPL 2017: 1-4 - [c22]Junqi Yuan, Lingli Wang, Xuegong Zhou, Yinshui Xia, Jianping Hu:
RBSA: Range-based simulated annealing for FPGA placement. FPT 2017: 1-8 - [c21]Moucheng Yang, Jifang Jin, Zhehao Li, Xuegong Zhou, Shaojun Wang, Lingli Wang:
A scalable hybrid architecture for high performance data-parallel applications. FPT 2017: 191-194 - 2016
- [c20]Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang:
A high performance FPGA-based accelerator for large-scale convolutional neural networks. FPL 2016: 1-9 - [c19]Qi Zhan, Min Gao, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang:
High performance Deformable Part Model accelerator based on FPGA. FPT 2016: 245-248 - 2015
- [c18]Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang:
An automated test framework for SRAM-based FPGA. ASICON 2015: 1-4 - [c17]Jian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Philip H. W. Leong, Lingli Wang:
UniStream: A unified stream architecture combining configuration and data processing. FPL 2015: 1-4 - [c16]Jifang Jin, Jian Yan, Xuegong Zhou, Lingli Wang:
An adaptive cross-layer fault recovery solution for reconfigurable SoCs. FPT 2015: 188-191 - 2013
- [j1]Ying Wang, Xuegong Zhou, Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng, Jiarong Tong:
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2179-2192 (2013) - [c15]Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan:
A reconfigurable floating-point FFT architecture. ASICON 2013: 1-4 - [c14]Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang, Lingli Wang:
Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA. FPT 2013: 152-159 - [c13]Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan, Lingli Wang:
A hardware implementation of Bag of Words and Simhash for image recognition. FPT 2013: 418-421 - [c12]Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang, Lingli Wang:
An FPGA-cluster-accelerated match engine for content-based image retrieval. FPT 2013: 422-425 - 2012
- [c11]Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong:
A partially reconfigurable architecture supporting hardware threads. FPT 2012: 269-276 - 2011
- [c10]Chaofan Yu, Lingli Wang, Xuegong Zhou:
Automatic layout generator for embedded FPGA cores. ASICON 2011: 385-388 - 2010
- [c9]Kejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D. Tan, Jiarong Tong:
General switch box modeling and optimization for FPGA routing architectures. FPT 2010: 320-323
2000 – 2009
- 2007
- [c8]Xuegong Zhou, Liang Liang, Ying Wang, Chenglian Peng:
Online Task Scheduling for Heterogeneous Reconfigurable Systems. CSCWD (Selected Papers) 2007: 596-607 - [c7]Liang Liang, Xuegong Zhou, Ying Wang, Chenglian Peng:
Online Hybrid Task Scheduling in Reconfigurable Systems. CSCWD 2007: 1072-1077 - [c6]Xuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng:
Fast On-line Task Placement and Scheduling on Reconfigurable Devices. FPL 2007: 132-138 - 2006
- [c5]Ying Wang, Xuegong Zhou, Bo Zhou, Liang Liang, Chenglian Peng:
A MDA based SoC Modeling Approach using UML and SystemC. CIT 2006: 245 - [c4]Xuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng:
On-line scheduling of real-time tasks for reconfigurable computing system. FPT 2006: 57-64 - [c3]Liang Liang, Bo Zhou, Xuegong Zhou, Chenglian Peng:
System Prototyping Based on SystemC Transaction-Level Modeling. IMSCCS (2) 2006: 764-770 - 2005
- [c2]Xuegong Zhou, Yan Chen, Liang Liang, Chenglian Peng, Hao Shen, Jingyao Zhang:
ESIDE - embedded system integrated design environment based on Eclipse platform. CSCWD (1) 2005: 113-117 - 2004
- [c1]Yan Chen, Xuan Du, Xuegong Zhou, Chenglian Peng:
An Automatic Coverage Analysis for SystemC Using UML and Aspect-Oriented Technology. CSCWD (Selected papers) 2004: 398-405
Coauthor Index
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