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Che-Hsun Kuo
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2010 – 2019
- 2015
- [j1]Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin:
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS. IEEE J. Solid State Circuits 50(11): 2645-2654 (2015) - [c2]Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, Chun-Jen Chen:
A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems. ISCAS 2015: 2425-2428 - 2014
- [c1]Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo:
A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. ISCAS 2014: 2345-2348
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last updated on 2025-01-07 01:23 CET by the dblp team
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