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M. Hesener

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2007
[c1]
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M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske:
A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS. ISSCC 2007: 248-600

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