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2020 – today
- 2023
[c4]Wei-Hsin Tseng, Willy Lin, Chung-Wei Hsu, Chang-Yang Huang, Yu-Sian Lin, Hung-Yi Huang, HsinWei Chen, Sheng-Hui Liao, Kuan-Dar Chen, Jon Strange, Gabriele Manganaro:
A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. ISSCC 2023: 268-269- 2021
- [j3]Hung-Yi Huang
, Xin-Yu Chen, Tai-Haur Kuo:
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone. IEEE J. Solid State Circuits 56(10): 3145-3156 (2021) - 2020
- [j2]Hung-Yi Huang, Tai-Haur Kuo:
A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing. IEEE J. Solid State Circuits 55(9): 2478-2488 (2020) - [c3]Shih-Hsiung Chien, Tai-Haur Kuo, Hung-Yi Huang, Hong-Bin Wang, Yi-Zhi Qiu:
23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction. ISSCC 2020: 352-354 - [c2]Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo:
A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c1]Hung-Yi Huang, Tai-Haur Kuo:
A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation. VLSI Circuits 2019: 136- - 2014
- [j1]Wei-Te Lin, Hung-Yi Huang, Tai-Haur Kuo:
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique. IEEE J. Solid State Circuits 49(3): 708-717 (2014)
Coauthor Index
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