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ORCIDJens Spinner
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2010 – 2019
- 2019
[b1]Jens Spinner:
Channel Coding for Flash Memories. University of Konstanz, Germany, 2019- 2018
- [j5]Jens Spinner, Daniel Rohweder, Jürgen Freudenberger
:
Soft input decoder for high-rate generalised concatenated codes. IET Circuits Devices Syst. 12(4): 432-438 (2018) - 2017
- [c8]Jens Spinner, Jürgen Freudenberger:
A decoder with soft decoding capability for high-rate generalized concatenated codes with applications in non-volatile flash memories. SBCCI 2017: 185-190 - 2016
- [j4]Jens Spinner, Jürgen Freudenberger, Sergo Shavgulidze:
A Soft Input Decoding Algorithm for Generalized Concatenated Codes. IEEE Trans. Commun. 64(9): 3585-3595 (2016) - 2015
- [j3]Jens Spinner, Jürgen Freudenberger:
Decoder architecture for generalised concatenated codes. IET Circuits Devices Syst. 9(5): 328-335 (2015) - [c7]Jürgen Freudenberger, Thomas Wegmann, Jens Spinner:
An efficient hardware implementation of sequential stack decoding of binary block codes. ICCE-Berlin 2015: 135-138 - 2014
- [j2]Jürgen Freudenberger, Jens Spinner, Sergo Shavgulidze:
Set partitioning of Gaussian integer constellations and its application to two-dimensional interleaving. IET Commun. 8(8): 1336-1346 (2014) - [j1]Jürgen Freudenberger, Jens Spinner:
A Configurable Bose-Chaudhuri-Hocquenghem codec Architecture for Flash controller Applications. J. Circuits Syst. Comput. 23(2) (2014) - [c6]Jürgen Freudenberger, Jens Spinner, Sergo Shavgulidze:
Generalized concatenated codes for correcting two-dimensional clusters of errors and independent errors. SSD 2014: 1-5 - [c5]Jürgen Freudenberger, Jens Spinner, Sergo Shavgulidze:
Set partitioning of Gaussian integer constellations and its application to two-dimensional interleaver design. SSD 2014: 1-5 - [c4]Jens Spinner, Jürgen Freudenberger:
Design and Implementation of a Pipelined Decoder for Generalized Concatenated Codes Format. SBCCI 2014: 35:1-35:6 - 2013
- [c3]Jens Spinner, Jürgen Freudenberger, Christoph Baumhof, Axel Mehnert, Richard Willems:
A BCH decoding architecture with mixed parallelization degrees for flash controller applications. SoCC 2013: 116-121 - 2012
- [c2]Jürgen Freudenberger, Uwe Kaiser, Jens Spinner:
Concatenated code constructions for error correction in non-volatile memories. ISSSE 2012: 1-6 - [c1]Jürgen Freudenberger, Jens Spinner:
Mixed serial/parallel hardware implementation of the Berlekamp-Massey algorithm for BCH decoding in Flash controller applications. ISSSE 2012: 1-5
Coauthor Index
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