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Ibtissem Seghaier
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2020 – today
- 2020
- [j2]Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 294-307 (2020)
2010 – 2019
- 2018
- [c7]Ibtissem Seghaier, Sofiène Tahar:
Discriminating Chaos from Non-Gaussian Noise on Analog Circuits. NEWCAS 2018: 26-30 - [c6]Ibtissem Seghaier, Sofiène Tahar:
Reliability Analysis of CMOS Rambus Oscillator under Device Mismatch Effects. NEWCAS 2018: 209-212 - 2017
- [c5]Ibtissem Seghaier, Sofiène Tahar:
Intertwined Global Optimization Based Reachability Analysis. VECoS 2017: 139-154 - 2016
- [c4]Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
Cross recurrence verification technique for process variation-resilient analog circuits. ISCAS 2016: 1294-1297 - 2015
- [c3]Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs. ACM Great Lakes Symposium on VLSI 2015: 99-102 - [c2]Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
A Statistical Approach to Probe Chaos from Noise in Analog and Mixed Signal Designs. ISVLSI 2015: 237-242 - 2014
- [c1]Ibtissem Seghaier, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar:
A qualitative simulation approach for verifying PLL locking property. ACM Great Lakes Symposium on VLSI 2014: 317-322 - 2013
- [j1]Rajeev Narayanan, Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1811-1822 (2013)
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