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ORCIDKonrad Möller
Person information
- affiliation: University of Kassel, Germany
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2010 – 2019
- 2019
[j4]Mario Garrido
, Konrad Möller, Martin Kumm:
World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1507-1516 (2019)- [c9]Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf:
Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. FPGA 2019: 43-52 - 2018
- [j3]Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf:
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 710-714 (2018) - [c8]Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch:
ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL 2018: 265-271 - 2017
- [b1]Konrad Möller:
Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays. University of Kassel, Germany, 2017, ISBN 978-3-7376-0376-8, pp. 1-116 - [j2]Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf:
Reconfigurable Constant Multiplication for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 927-937 (2017) - [c7]Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis:
Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT 2017: 199-202 - [c6]Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf:
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV 2017: 103-114 - 2015
- [i1]Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf:
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. CoRR abs/1508.06811 (2015) - 2014
- [c5]Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf:
Pipelined reconfigurable multiplication with constants on FPGAs. FPL 2014: 1-6 - [c4]Konrad Möller, Martin Kumm, Björn Barschtipan, Peter Zipf:
Dynamically Reconfigurable Constant Multiplication on FPGAs. MBMV 2014: 159-169 - 2013
- [j1]Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf, Uwe Meyer-Baese:
FIR filter optimization for video processing on FPGAs. EURASIP J. Adv. Signal Process. 2013: 111 (2013) - [c3]Martin Kumm, Konrad Möller, Peter Zipf:
Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. ISCAS 2013: 2054-2057 - [c2]Martin Kumm, Konrad Möller, Peter Zipf:
Reconfigurable FIR filter using distributed arithmetic on FPGAs. ISCAS 2013: 2058-2061 - [c1]Martin Kumm, Konrad Möller, Peter Zipf:
Dynamically reconfigurable FIR filter architectures with fast reconfiguration. ReCoSoC 2013: 1-8
Coauthor Index
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