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2010 – 2019
- 2019
[c6]Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang:
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. NOCS 2019: 16:1-16:8- 2018
- [j6]Yilei Li
, Kirti Dhwaj, Chien-Heng Wong, Yuan Du, Li Du, Yiwu Tang, Yiyu Shi, Tatsuo Itoh, Mau-Chung Frank Chang:
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 146-158 (2018) - [j5]X. Shawn Wang, Xin Jin, Jieqiong Du, Yilei Li, Yuan Du, Chien-Heng Wong, Yen-Cheng Kuan, Chi-Hang Chan, Mau-Chung Frank Chang:
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1534-1538 (2018) - [c5]Yiwu Tang, Chien-Heng Wong, Yuan Du, Li Du, Yilei Li, Mau-Chung Frank Chang:
A fully integrated 28nm CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mv startup voltage. CICC 2018: 1-4 - 2017
- [j4]Yuan Du, Wei-Han Cho, Po-Tsang Huang, Yilei Li, Chien-Heng Wong, Jieqiong Du, Yanghyo Kim, Boyu Hu, Li Du, Chun-Chen Liu, Sheau Jiung Lee, Mau-Chung Frank Chang:
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection. IEEE J. Solid State Circuits 52(4): 1111-1122 (2017) - [j3]Zuow-Zun Chen, Yen-Cheng Kuan, Yilei Li, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang:
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers. IEEE J. Solid State Circuits 52(4): 1134-1143 (2017) - 2016
- [j2]Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee:
A 200-MS/s Phase-Detector-Based Comparator With 400-μVrms Noise. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 813-817 (2016) - [c4]Chun-Chen Liu, Yen-Hsiang Wang, Yilei Li, Chien-Heng Wong, Tien Pei Chou, Young-Kai Chen, M.-C. Frank Chang:
Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm. DAC 2016: 2:1-2:6 - [c3]Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. ISSCC 2016: 184-185 - [c2]Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang:
Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers. VLSI Circuits 2016: 1-2 - [c1]Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang:
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2013
- [j1]Chien-Heng Wong, Tai-Cheng Lee:
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1264-1273 (2013)
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