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Michael Ashburn

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2010 – 2019

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2019
[c5]
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  dblp key:
  - conf/cicc/ShabraCCBHA19
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  - https://dblp.org/rec/conf/cicc/ShabraCCBHA19
Ayman Shabra, Padraig Cooney, Adalberto Cantoni, Joshua Bamford, Stacy Ho, Michael Ashburn:
A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD. CICC 2019: 1-4
2018
[c4]
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  - conf/isscc/HeAHZT18
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Tao He, Michael Ashburn, Stacy Ho, Yi Zhang, Gabor C. Temes:
A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. ISSCC 2018: 230-232
2017
[c3]
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  - conf/isscc/HuangEKOA17
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Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn:
28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS. ISSCC 2017: 470-471
2013
[c2]
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  - conf/isscc/RiehlFHA13
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Patrick Riehl, Paul Fowers, Hao-Ping Hong, Michael Ashburn:
An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency. ISSCC 2013: 364-365
[c1]
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  - conf/isscc/KaoLCA13
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Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn:
A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation. ISSCC 2013: 416-417

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