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2020 – today
- 2023
[j3]Yonggeun Cho
, Seokchang Hong, Kiyeon Lee:
Scattering and Nonscattering of the Hartree-Type Nonlinear Dirac System at Critical Regularity. SIAM J. Math. Anal. 55(4): 3395-3419 (2023)
2010 – 2019
- 2013
- [j2]Kiyeon Lee, Sangyeun Cho:
Accurately modeling superscalar processor performance with reduced trace. J. Parallel Distributed Comput. 73(4): 509-521 (2013) - 2012
- [c7]Kiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon-Gon Cho, Sangyeun Cho:
Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors. ICCD 2012: 500-501 - 2011
- [c6]Kiyeon Lee, Sangyeun Cho:
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. MASCOTS 2011: 126-135 - [c5]Taecheol Oh, Kiyeon Lee, Sangyeun Cho:
An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. MASCOTS 2011: 150-158 - 2010
- [j1]Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho:
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. Softw. Pract. Exp. 40(3): 239-258 (2010)
2000 – 2009
- 2009
- [c4]Kiyeon Lee, Shayne Evans, Sangyeun Cho:
Accurately approximating superscalar processor performance from traces. ISPASS 2009: 238-248 - [c3]Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho:
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. ISVLSI 2009: 181-186 - 2008
- [c2]Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng:
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. ICPP 2008: 446-453 - 2007
- [c1]Sangyeun Cho, Lei Jin, Kiyeon Lee:
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. RTCSA 2007: 3-11
Coauthor Index
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