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2000 – 2009
- 2001
[c8]Jun Cao, Belle W. Y. Wei, Jie Cheng:
High-Performance Architectures for Elementary Function Generation. IEEE Symposium on Computer Arithmetic 2001: 136-
1990 – 1999
- 1997
- [c7]Jun Cao, Belle W. Y. Wei:
High-Performance Hardware for Function Generation. IEEE Symposium on Computer Arithmetic 1997: 184- - 1995
- [j5]Belle W. Y. Wei, Teresa H. Meng:
A parallel decoder of programmable Huffman codes. IEEE Trans. Circuits Syst. Video Technol. 5(2): 175-178 (1995) - [c6]Belle W. Y. Wei, He Du, Honglu Chen:
A complex-number multiplier using radix-4 digits. IEEE Symposium on Computer Arithmetic 1995: 84- - 1994
- [j4]K. Tsang, Belle W. Y. Wei:
A VLSI architecture for a real-time code book generator and encoder of a vector quantizer. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 360-364 (1994) - [c5]Belle W. Y. Wei, Wen H. Chen:
Video coding for HDTV systems. COMPSAC 1994: 469-475 - [c4]Belle W. Y. Wei, Teresa H.-Y. Meng:
A Programmable Parallel Huffman Decoder. ICIP (3) 1994: 668-671 - 1993
- [c3]Belle W. Y. Wei, Richard Tarver, Jong-Seop Kim, Kevin Ng:
A Single Chip Lempel-Ziv Data Compressor. ISCAS 1993: 1953-1955 - 1991
- [j3]Clark D. Thomborson
, Belle W. Y. Wei:
Systolic implementations of a move-to-front text compressor. SIGARCH Comput. Archit. News 19(1): 53-60 (1991) - [j2]Xiaoping Huang, Belle W. Y. Wei, Honglu Chen, Yuhai H. Mao:
High-performance VLSI multiplier with a new redundant binary coding. J. VLSI Signal Process. 3(4): 283-291 (1991) - 1990
- [j1]Belle W. Y. Wei, Clark D. Thompson:
Area-Time Optimal Adder Design. IEEE Trans. Computers 39(5): 666-675 (1990)
1980 – 1989
- 1989
- [c2]Clark D. Thomborson, Belle W. Y. Wei:
Systolic Implementations of a Move-to-Front Text Compressor. SPAA 1989: 283-290 - 1988
- [c1]Yuh Yaw, Belle W. Y. Wei, C. V. Ramamoorthy, Wei-Tek Tsai:
Extensions on performance evaluation techniques for concurrent systems. COMPSAC 1988: 480-484
Coauthor Index
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