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Journal Articles
- 2016
[j3]Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang:
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1189-1192 (2016)- 2015
- [j2]Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Leakage Power. ACM Trans. Design Autom. Electr. Syst. 21(1): 9:1-9:33 (2015) - 2014
- [j1]Shih-Hsu Huang, Hua-Hsin Yeh:
Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1699-1708 (2014)
Conference and Workshop Papers
- 2014
- [c5]Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang:
Live demonstration: A low-power high-level synthesis system. APCCAS 2014: 165-166 - [c4]Hua-Hsin Yeh, Wen-Pin Tu, Jian-Zhi Shen, Tung-Hua Yen, Shih-Hsu Huang:
Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. APCCAS 2014: 611-614 - [c3]Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh:
Leakage-power-aware clock period minimization. DATE 2014: 1-6 - 2012
- [c2]Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng:
A formal approach to slack-driven high-level synthesis. ISCAS 2012: 584-587 - 2011
- [c1]Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng:
Teaching three-dimensional system-in-package design automation in a semester course. MSE 2011: 52-55
Coauthor Index
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