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Journal Articles
- 2024
[j5]Sigang Ryu
, Jaeha Kim, Arijit Raychowdhury:
Fractionally-Spaced Equalizers as Clock and Data Recovery Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3002-3015 (2024)- 2021
- [j4]Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim:
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2876-2889 (2021) - 2019
- [j3]Seuk Son, Sigang Ryu, Hwanseok Yeo, Jaeha Kim:
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery. IEEE J. Solid State Circuits 54(10): 2823-2832 (2019) - [j2]Sigang Ryu, Seuk Son, Jaeha Kim:
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1245-1257 (2019) - 2014
- [j1]Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function. IEEE J. Solid State Circuits 49(8): 1773-1784 (2014)
Conference and Workshop Papers
- 2024
- [c8]Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC 2024: 482-484 - [c7]Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury:
A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c6]Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu, Arijit Raychowdhury:
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems. ACM Great Lakes Symposium on VLSI 2023: 631-637 - [c5]Sigang Ryu, Adou Sangbone Assoa, Shota Konno, Arijit Raychowdhury:
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications. VLSI Technology and Circuits 2023: 1-2 - 2018
- [c4]Seuk Son, Hwanseok Yeo, Sigang Ryu, Jaeha Kim:
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery. A-SSCC 2018: 201-204 - 2016
- [c3]Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, Jaeha Kim:
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications. ISSCC 2016: 238-239 - 2013
- [c2]Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2-GHz digital phase-locked loop with peaking-free transfer function. CICC 2013: 1-4 - 2012
- [c1]Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong:
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. ISCAS 2012: 754-757
Coauthor Index
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