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ORCIDSushmita Kadiyala Rao
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2010 – 2019
- 2015
[c7]Sushmita Kadiyala Rao, Deepak Krishnankutty, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Post-layout estimation of side-channel power supply signatures. HOST 2015: 92-95- [c6]Bharath Shivashankar, Michael Skaggs, Sushmita Kadiyala Rao, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Estimation of dynamic current waveforms using pre-characterization of standard cells. LATS 2015: 1-6 - [c5]Michael Skaggs, Sushmita Kadiyala Rao, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Transient current estimation using S3C (Standard cell current transient characterization). VDAT 2015: 1-6 - [c4]Sushmita Kadiyala Rao, Bharath Shivashankar, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Scalability study of PSANDE: Power supply analysis for noise and delay estimation. VTS 2015: 1-6 - 2014
- [j1]Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay. J. Electron. Test. 30(1): 125-147 (2014) - 2013
- [c3]Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
Framework for dynamic estimation of power-supply noise and path delay. DFTS 2013: 272-277 - [c2]Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
Scalable dynamic technique for accurately predicting power-supply noise and path delay. VTS 2013: 1-6 - 2012
- [c1]Sushmita Kadiyala Rao, Chaitra Sathyanarayana, Ajay Kallianpur, Ryan W. Robucci, Chintan Patel:
Estimating Power Supply Noise and its impact on path delay. VTS 2012: 276-281
Coauthor Index
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