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Sudip Ghosh 0001
Person information
- affiliation (PhD 2017): Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India
Other persons with the same name
- Sudip Ghosh 0002 — Université de Bordeaux, Talence, France
- Sudip Ghosh 0003 — Machine Intelligence Unit, Kolkata, India
- Sudip Ghosh 0004 — Dr. B. C. Roy Engineering College, Durgapur, India
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Journal Articles
- 2022
- [j4]Sudip Ghosh, Yuvam Bhateja, Joshua Roy Palathinkal, Hafizur Rahaman:
Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR. Circuits Syst. Signal Process. 41(2): 867-891 (2022) - 2018
- [j3]Subhajit Das, Sudip Ghosh, Nachiketa Das, Santi P. Maity, Hafizur Rahaman, Reshmi Maity, Niladri Maity:
Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach. Circuits Syst. Signal Process. 37(12): 5690 (2018) - [j2]Sambaran Hazra, Sudip Ghosh, Sayandip De, Hafizur Rahaman:
FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time. J. Real Time Image Process. 14(1): 193-221 (2018) - 2015
- [j1]Sudip Ghosh, Arijit Biswas, Santi Prasad Maity, Hafizur Rahaman:
Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications. J. Low Power Electron. 11(3): 375-386 (2015)
Conference and Workshop Papers
- 2023
- [c10]Piyali Saha, Sudip Ghosh, Debajyoti Pal, Hafizur Rahaman:
Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC. IAIT 2023: 1:1-1:7 - [c9]Anchit Arun, Ananya Chakraborty, Priyanka Dutta, Debajyoti Pal, Tridibesh Nag, Debasis De, Sudip Ghosh, Hafizur Rahaman:
Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra. IAIT 2023: 23:1-23:6 - [c8]Rounak Roy, Sudip Ghosh, Hafizur Rahaman:
Implementation of Area Efficient Adders for Inexact Computing. ISDCS 2023: 1-4 - 2020
- [c7]Joshua Roy Palathinkal, Yuvam Bhateja, Sudip Ghosh, Hafizur Rahaman:
A New Blind Invisible and Semi-Fragile Colour Image Watermarking Scheme in Spatial Domain. ISDCS 2020: 1-6 - [c6]Shivdeep, Sudip Ghosh, Hafizur Rahaman:
A New Digital Color Image Watermarking Algorithm with its FPGA and ASIC Implementation. ISDCS 2020: 1-6 - 2016
- [c5]Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das:
A rule-based approach for minimizing power dissipation of digital circuits. DDECS 2016: 237-242 - 2015
- [c4]Sudip Ghosh, Nachiketa Das, Subhajit Das, Santi Prasad Maity, Hafizur Rahaman:
An adaptive feedback based reversible watermarking algorithm using difference expansion. ReTIS 2015: 207-212 - 2014
- [c3]Sudip Ghosh, Nachiketa Das, Subhajit Das, Santi P. Maity, Hafizur Rahaman:
Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA. ICIT 2014: 123-128 - [c2]Sudip Ghosh, Arijit Biswas, Santi P. Maity, Hafizur Rahaman:
Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA. ISED 2014: 68-72 - 2012
- [c1]Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, Santi P. Maity:
VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark. VDAT 2012: 375-376
Coauthor Index
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