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ORCIDYidong Chen 0005
Person information
- affiliation: University of Washington, Department of Electrical and Computer Engineering, Seattle, WA, USA
Other persons with the same name
- Yidong Chen 0001
![[0000-0002-0243-7228]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-0243-7228")
— Xiamen University, School of Informatics, Department of Artificial Intelligence, China (and 1 more) - Yidong Chen 0002 — University of Texas Health Science Center at San Antonio, Department of Epidemiology and Biostatistics, TX, USA (and 2 more)
- Yidong Chen 0003 — Chinese Academy of Sciences, Computer Network Information Center, Beijing, China (and 1 more)
- Yidong Chen 0004 — State Grid Hunan Electric Power Company Limited Economic & Technical Research Institute, Changsha, China (and 1 more)
- Yidong Chen 0006 — Jimei University, Computer Engineering College, Xiamen, China
- Yidong Chen 0007 — Sichuan University, College of Electrical Engineering, Chengdu, China
- Yidong Chen 0008 — Peking University Third Hospital, Department of Obstetrics and Gynecology, Beijing, China
- Yidong Chen 0009 — Peking University, Beijing, China
- Yidong Chen 0010 — Shanghai Jiaotong University, Shanghai Key Laboratory of Scalable Computing and Systems, China
- Yidong Chen 0011 — South China University of Technology, Automation Department, Guangzhou, China
- Yidong Chen 0012 — Beijing University of Posts and Telecommunications, State Key Laboratory of Information Photonics and Optical Communications, China
- Yidong Chen 0013 — ByteDance Inc., Shenzhen, China
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Journal Articles
- 2022
[j1]Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe:
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57(1): 90-102 (2022)
Conference and Workshop Papers
- 2021
- [c1]Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe:
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. ISSCC 2021: 416-418
Coauthor Index
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