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ORCIDXiaofeng Yang 0006
Person information
- affiliation: Xi'an University of Post & Telecommunication, China
Other persons with the same name
- Xiaofeng Yang — disambiguation page
- Xiaofeng Yang 0001
![[0009-0006-3289-2025]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0009-0006-3289-2025")
— Tencent, Shenzhen, China (and 1 more) - Xiaofeng Yang 0002 — Chinese Academy of Sciences, Institute of Remote Sensing and Digital Earth, Beijing, China
- Xiaofeng Yang 0003 — University of South Carolina, Department of Mathematics, Columbia, SC, USA
- Xiaofeng Yang 0004 — University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Macau
- Xiaofeng Yang 0005 — Emory University, Department of Radiation Oncology and Winship Cancer Institute, Atlanta, GA, USA
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2020 – today
- 2023
[c9]Xiaofeng Yang, Gulin Chen:
Design and verification of SRAM controller based on FPGA. AIPR 2023: 868-873- [c8]Xiaofeng Yang, Chuang Wu:
Research on Spaceborne Memory Control Based on FPGA Configuration Refresh Technology. AIPR 2023: 874-879 - [c7]Xiaofeng Yang, Yongnian Jiang, Mingxi Ren:
Design and Verification of a High Performance Deserial Serial Peripheral Interface. AIPR 2023: 880-885 - [c6]Xin Li, Xiaofeng Yang:
Design of High Performance Dynamic DMA Based on Multidimensional Nesting Technology. AIPR 2023: 886-890 - [c5]Xiaofeng Yang, Pingyan Dong:
Design of 18-25GHz On-chip Double-balanced Passive Mixer. AIPR 2023: 1138-1142 - 2022
- [c4]Xiaofeng Yang, Ancheng Liu, Jinjin Wang:
High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM. AIPR 2022: 193-196 - [c3]Xiaofeng Yang, Jinjin Wang, Ancheng Liu:
Bad Block Detection of Spaceborne NAND Flash Based on FPGA. AIPR 2022: 839-845 - [c2]Xiaofeng Yang, Yaling Su:
Design of Communication Controller Chip Based on FlexRay Bus. AIPR 2022: 970-975 - [c1]Xiaofeng Yang, Chaochao Qiu:
Design and Implementation of Miniaturized Flight Control Computer Based on FPGA+DSP. AIPR 2022: 1141-1145
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