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ORCIDAndré Seffrin
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2010 – 2019
- 2012
[b1]André Seffrin:
A Process-Algebraic Approach to Security-Aware Scheduling of Dynamic Partial Reconfiguration on FPGA Devices. Darmstadt University of Technology, Verlag Dr. Hut 2012- [c10]André Seffrin, Sorin A. Huss:
Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). FPGA 2012: 267 - [c9]Florian Benz, André Seffrin, Sorin A. Huss:
Bil: A tool-chain for bitstream reverse-engineering. FPL 2012: 735-738 - 2011
- [c8]André Seffrin, Sorin A. Huss:
Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms. DDECS 2011: 457-462 - [c7]André Seffrin, Sorin A. Huss:
Hardware-accelerated execution of Pi-calculus reconfiguration schedules. FPT 2011: 1-8 - [c6]André Seffrin, Sorin A. Huss:
Determining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications. MBMV 2011: 193-202 - [c5]André Seffrin, Sorin A. Huss:
Ensuring Secure Information Flow in Partially Reconfigurable Architectures by Means of Process Algebra Analysis. TrustCom 2011: 443-450 - [c4]H. Gregor Molter
, André Seffrin, Sorin A. Huss:
State space optimization within the DEVS model of computation for timing efficiency. VLSI-SoC 2011: 422-427 - 2010
- [c3]André Seffrin, Alexander Biedermann, Sorin A. Huss:
Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes. FDL 2010: 86-91 - [c2]André Seffrin, Sunil Malipatlolla, Sorin A. Huss:
A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability. FPT 2010: 291-294
2000 – 2009
- 2009
- [c1]H. Gregor Molter, André Seffrin, Sorin Alexander Huss:
DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code. FDL 2009: 1-6
Coauthor Index
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