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2020 – today
- 2021
[j4]Yu-Ching Wu, Chia-I Chen, Peng-Ying Chen, Chun-Hung Kuo, Yi-Hsuan Hung, Kang-Yung Peng, Vin-Cent Wu, Jyy-Jih Tsai-Wu, Chia-Lang Hsu
:
GRAde: a long-read sequencing approach to efficiently identifying the CYP11B1/CYP11B2 chimeric form in patients with glucocorticoid-remediable aldosteronism. BMC Bioinform. 22-S(10): 613 (2021)
2010 – 2019
- 2014
- [c4]Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu:
Apply high-level synthesis design and verification methodology on floating-point unit implementation. VLSI-DAT 2014: 1-4 - 2012
- [j3]Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou:
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 559-566 (2012) - 2011
- [j2]Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu:
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1151-1155 (2011) - [c3]Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang:
Architectural exploration of 3D FPGAs towards a better balance between area and delay. DATE 2011: 587-590 - [c2]Chia-I Chen, Juinn-Dar Huang:
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. ISVLSI 2011: 369-370 - 2010
- [j1]Chia-I Chen, Juinn-Dar Huang:
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1300-1308 (2010)
2000 – 2009
- 2009
- [c1]Chia-I Chen, Juinn-Dar Huang:
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ASP-DAC 2009: 67-72
Coauthor Index
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