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ORCIDNagendra Dwarakanath Gulur
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2020 – today
- 2022
[c14]Shashank Adavally, Alex Weaver, Pranathi Vasireddy, Krishna Kavi, Gayatri Mehta, Nagendra Gulur:
HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA PROCESSING. IPDPS Workshops 2022: 6-15- 2020
- [c13]Harsh Gugale, Nagendra Gulur, Yashwant Marathe, Lizy K. John:
ATTC (@C): Addressable-TLB based Translation Coherence. PACT 2020: 481-492 - [c12]Shashank Adavally, Nagendra Gulur, Krishna Kavi, Alex Weaver, Pranoy Dutta, Benjamin Wang:
ExPress: Simultaneously Achieving Storage, Execution and Energy Efficiencies in Moderately Sparse Matrix Computations. MEMSYS 2020: 46-60 - [c11]Fernando Mosquera, Nagendra Gulur, Krishna Kavi, Gayatri Mehta, Hua Sun:
CHASM: Security Evaluation of Cache Mapping Schemes. SAMOS 2020: 245-261
2010 – 2019
- 2017
- [c10]Jee Ho Ryoo, Nagendra Gulur, Shuang Song, Lizy K. John:
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB. ISCA 2017: 469-480 - [c9]Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, Lizy K. John:
CSALT: context switch aware large TLB. MICRO 2017: 449-462 - [i1]Jayvant Anantpur, Nagendra Dwarakanath Gulur, Shivaram Kalyanakrishnan, Shalabh Bhatnagar, R. Govindarajan:
RLWS: A Reinforcement Learning based GPU Warp Scheduler. CoRR abs/1712.04303 (2017) - 2016
- [c8]Nagendra Gulur, R. Govindarajan, Mahesh Mehendale:
MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. MEMSYS 2016: 350-361 - 2015
- [c7]Nagendra Gulur, Narayanan L. Suriya:
Understanding the Performance Benefit of Asynchronous Data Transfers in OpenCL Programs Executing on Media Processors. HiPC 2015: 135-144 - [c6]Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan:
A Comprehensive Analytical Performance Model of DRAM Caches. ICPE 2015: 157-168 - 2014
- [c5]Vasant Easwaran, Nagendra Gulur, Sushaanth Srirangapathi, Mihir Mody, Rahul Gulati, Prashant Karandikar, Prithvi Shankar:
Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets. ISED 2014: 210-214 - [c4]Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan:
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. MICRO 2014: 38-50 - [c3]Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan:
ANATOMY: an analytical model of memory system performance. SIGMETRICS 2014: 505-517 - 2012
- [c2]Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan:
Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. ICS 2012: 257-266 - 2011
- [c1]Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale:
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT 2011: 189-190
Coauthor Index
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