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ORCIDKenji Ichijo
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2020 – today
- 2022
[c9]Shun Orita, Akiko Narita, Kenji Ichijo:
Design of Multicore Dataflow DSPs with Different Loop Iteration Mechanisms. ICCE-TW 2022: 109-110
2010 – 2019
- 2016
- [c8]Kenji Ichijo, Sora Deguchi, Akiko Narita:
Expansion of operations in a multicore dataflow DSP. ICCE-TW 2016: 1-2 - [c7]Wataru Yokota, Kenji Ichijo, Akiko Narita:
Evaluation of the Redundant Traffic Reduction Node Using the Packet Cache Coping with Different Byte Offsets among Streams. NaNA 2016: 227-232 - [c6]Tomohiro Yoshida, Yamato Ikeda, Kenji Ichijo, Akiko Narita:
Autonomous Decision of Function of the Redundant Traffic Reduction Node Using a New IP Option. NaNA 2016: 233-238 - 2013
- [j1]Hiroyuki Ogata, Kenji Ichijo, Kenji Kondo, Akito Hara:
Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate. IEICE Trans. Electron. 96-C(2): 285-288 (2013) - 2010
- [c5]Akiko Narita, Kenji Ichijo, Yoshio Yoshioka:
Comprehensive Evaluation of Packet Flow Control Methods for a Ring Nework of Processors on Chip. ACIS-ICIS 2010: 75-80 - [c4]Tomoyuki Nagase, Kenji Ichijo, Akiko Narita, Yoshio Yoshioka:
CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis. DFT 2010: 109-114 - [c3]Tatsuya Suto, Kenji Ichijo, Yoshio Yoshioka:
Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System. DFT 2010: 172-179 - [c2]Akiko Narita, Kenji Ichijo, Yoshio Yoshioka:
Evaluation of Packet Flow Control Methods for a LSC on Chip with Hardware Requirements and Performance. PDPTA 2010: 390-396
2000 – 2009
- 2003
- [c1]Kenji Ichijo, Yoshio Yoshioka:
Efficient Implementation of the Vector Operation on the Loop Structured Computer. PDPTA 2003: 338-344
Coauthor Index
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