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2010 – 2019
- 2018
[c5]Chen-Yen Ho, Shih-Mei Lin, Che-Hao Meng, Hao-Ping Hong, Sheng-Hong Yan, Ting-Hsun Kuo, Chia-Sheng Peng, Chieh-Hsun Hsiao, Hsin-Hung Chen, Da-Wei Sung, Chien-Wei Kuan:
An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOS. ISSCC 2018: 432-434- 2015
- [j3]Chen-Yen Ho, Cong Liu, Chi-Lun Lo, Hung-Chieh Tsai, Tze-Chien Wang, Yu-Hsin Lin:
A 4.5 mW CT Self-Coupled ΔΣ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation. IEEE J. Solid State Circuits 50(12): 2870-2879 (2015) - [c4]Chen-Yen Ho, Cong Liu, Chi-Lun Lo, Hung-Chieh Tsai, Tze-Chien Wang, Yu-Hsin Lin:
15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation. ISSCC 2015: 1-3 - 2014
- [c3]Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, Bo Hu, Jun Zha, Steven Chuang:
A power management unit integrated ADSL/ADSL2+ CPE analog front-end with -93.5dB THD for DMT-based applications. A-SSCC 2014: 113-116 - 2013
- [j2]Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho, Yu-Hsin Lin:
A 64-fJ/Conv.-Step Continuous-Time Sigma Delta Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital Delta Sigma Truncator. IEEE J. Solid State Circuits 48(11): 2637-2648 (2013) - 2011
- [j1]Chen-Yen Ho, Wei-Shan Chan, Yung-Yu Lin, Tsung-Hsien Lin
:
A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. IEEE J. Solid State Circuits 46(11): 2571-2582 (2011) - [c2]Chen-Yen Ho, Zwei-Mei Lee, Mu-Chen Huang, Sheng-Jui Huang:
A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application. A-SSCC 2011: 261-264 - 2010
- [c1]Chen-Yen Ho, Yung-Yu Lin, Tsung-Hsien Lin:
Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. ISCAS 2010: 25-28
Coauthor Index
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