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2020 – today
- 2020
[i1]Hongbin Zheng, Sejong Oh, Huiqing Wang, Preston Briggs, Jiading Gai, Animesh Jain, Yizhi Liu, Rich Heaton, Randy Huang, Yida Wang:
Optimizing Memory-Access Patterns for Deep Learning Accelerators. CoRR abs/2002.12798 (2020)
2010 – 2019
- 2014
- [j1]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
:
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1832-1845 (2014) - [c5]Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Fast and effective placement and routing directed high-level synthesis for FPGAs. FPGA 2014: 1-10 - [c4]Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
New solutions for system-level and high-level synthesis (Invited paper). ISIC 2014: 71-74 - 2013
- [c3]Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang:
A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis. ASP-DAC 2013: 780-786 - [c2]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow:
High-level synthesis with behavioral level multi-cycle path analysis. FPL 2013: 1-8 - 2011
- [c1]Guanwen Zhong, Hongbin Zheng, ZhenHua Jin, Dihu Chen, Zhiyong Pang:
1024-point pipeline FFT processor with pointer FIFOs based on FPGA. VLSI-SoC 2011: 122-125
Coauthor Index
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