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ORCIDKwanyeob Chae
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Journal Articles
- 2024
[j4]Kwanyeob Chae
, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin:
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. IEEE J. Solid State Circuits 59(1): 231-242 (2024)- 2014
- [j3]Kwanyeob Chae, Saibal Mukhopadhyay:
A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 74-83 (2014) - [j2]Kwanyeob Chae, Saibal Mukhopadhyay:
Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 173-177 (2014) - 2012
- [j1]Kwanyeob Chae, Saibal Mukhopadhyay:
All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 893-897 (2012)
Conference and Workshop Papers
- 2023
- [c13]Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin:
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. ISSCC 2023: 406-407 - 2020
- [c12]Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim, Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyounghoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park:
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. ISSCC 2020: 338-340 - 2019
- [c11]Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko:
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. VLSI Circuits 2019: 96- - 2018
- [c10]Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park:
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. ISOCC 2018: 140-141 - 2017
- [c9]Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park:
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. ISSCC 2017: 398-399 - 2016
- [c8]Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee:
A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. ESSCIRC 2016: 461-464 - 2013
- [c7]Kwanyeob Chae, Saibal Mukhopadhyay:
Error resilient logic circuits under dynamic variations. IOLTS 2013: 250 - [c6]Denny Lie, Kwanyeob Chae, Saibal Mukhopadhyay:
On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing. NANOARCH 2013: 128-133 - 2012
- [c5]Kwanyeob Chae, Saibal Mukhopadhyay:
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs. ASP-DAC 2012: 277-282 - [c4]Minki Cho, Muhammad M. Khellah, Kwanyeob Chae, Khondker Zakir Ahmed, James W. Tschanz, Saibal Mukhopadhyay:
Characterization of Inverse Temperature Dependence in logic circuits. CICC 2012: 1-4 - [c3]Kwanyeob Chae, Minki Cho, Saibal Mukhopadhyay:
Low-power design under variation using error prevention and error tolerance (invited paper). LATW 2012: 1-6 - 2010
- [c2]Kwanyeob Chae, Saibal Mukhopadhyay, Chang-Ho Lee, Joy Laskar:
A dynamic timing control technique utilizing time borrowing and clock stretching. CICC 2010: 1-4 - 2004
- [c1]Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim:
High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study. DATE 2004: 538-543
Coauthor Index
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