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Mamoru Sugie
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Journal Articles
- 2004
- [j4]Yutaka Yoshimura, Toshiaki Tarui, Toru Shonai, Shun Kawabe, Mamoru Sugie:
Server-allocation policy for improving response to web-access peaks. Syst. Comput. Jpn. 35(5): 55-66 (2004) - 1994
- [j3]Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie:
A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability. IEEE Trans. Parallel Distributed Syst. 5(11): 1169-1184 (1994) - 1992
- [j2]Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie:
Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers. Parallel Comput. 18(10): 1079-1103 (1992) - 1980
- [j1]Yuzo Kita, Noboru Yamaguchi, Mamoru Sugie, Shigeru Yoshizawa:
The Development of a Bubble Memory Controller for Low-Cost File Use. IEEE Trans. Computers 29(2): 89-96 (1980)
Conference and Workshop Papers
- 2003
- [c8]Mineyoshi Masuda, Yutaka Yoshimura, Toshiaki Tarui, Toru Shonai, Mamoru Sugie:
VPDC: Virtual Private Data Center: A Flexible and Rapid Workloadmanagement System. Integrated Network Management 2003: 473-476 - 2000
- [c7]Aki W. Tomita, Naoki Watanabe, Yoshifumi Takamoto, Shigekazu Inohara, Frederico B. Maciel, Hiroaki Odawara, Mamoru Sugie:
A Scalable, Cost-Effective, and Flexible Disk System Using High-Performance Embedded-Processors. ICPP 2000: 317-326 - 1994
- [c6]Toshiaki Tarui, Machiko Asaie, Noriyasu Ido, Takayuki Nakagawa, Mamoru Sugie:
Evaluation of the Cluster Structure on the PIM/C Parallel Interface Machine. ICPP (2) 1994: 309-313 - 1992
- [c5]Takayuki Nakagawa, Noriyasu Ido, Toshiaki Tarui, Machiko Asaie, Mamoru Sugie:
Hardware Implementation of Dynamic Load Balancing in the Parallel Inference Machine PIM/c. FGCS 1992: 723-730 - [c4]Toshiaki Tarui, Takayuki Nakagawa, Noriyasu Ido, Machiko Asaie, Mamoru Sugie:
Evaluation of the lock mechanism in a snooping cache. ICS 1992: 53-62 - 1991
- [c3]Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie:
A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability. ITC 1991: 758-767 - 1988
- [c2]Mamoru Sugie, M. Yoneyama, Noriyasu Ido, Toshiaki Tarui:
Load-Dispatching Strategy on Parallel Inference Machines. FGCS 1988: 987-993 - 1985
- [c1]Mamoru Sugie, M. Yoneyama, T. Sakabe, M. Iwasaki, S. Yoshizumi, Moritoshi Aso, Hajime Shimizu, Rikio Onai:
Hardware Simulator of Reduction-Based Parallel Inference Machine PIM-R. LP 1985: 13-24
Coauthor Index
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