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ORCIDKlaus Eckl
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2000 – 2009
- 2003
[b1]Klaus Eckl:
Technologienahe Retimingverfahren zur Optimierung synchroner digitaler Schaltungen. Technical University Munich, 2003, ISBN 3-89791-317-8, pp. 1-110- [c7]Ulrich Seidl, Klaus Eckl, Frank M. Johannes:
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information. DATE 2003: 10770-10777
1990 – 1999
- 1999
- [j2]Bernd Wurth, Ulf Schlichtmann
, Klaus Eckl, Kurt Antreich:
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 4(3): 313-350 (1999) - [c6]Klaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl:
A Practical Approach to Multiple-Class Retiming. DAC 1999: 237-242 - [c5]Klaus Eckl, Christian Legl:
Retiming Sequential Circuits with Multiple Register Classes. DATE 1999: 650- - 1998
- [j1]Christian Legl, Bernd Wurth, Klaus Eckl:
Computing support-minimal subfunctions during functional decomposition. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 354-363 (1998) - 1996
- [c4]Christian Legl, Bernd Wurth, Klaus Eckl:
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs. DAC 1996: 730-733 - [c3]Christian Legl, Bernd Wurth, Klaus Eckl:
An Implicit Algorithm for Support Minimization during Functional Decomposition. ED&TC 1996: 412-419 - [c2]Christian Legl, Klaus Eckl, Bernd Wurth:
Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play? FPL 1996: 14-23 - 1995
- [c1]Bernd Wurth, Klaus Eckl, Kurt Antreich:
Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm. DAC 1995: 54-59
Coauthor Index
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