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Journal Articles
- 2018
[j2]Nimish Shah, Paragkumar Chaudhari, Kuruvilla Varghese
:
Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 29(12): 5922-5934 (2018)- 2015
- [j1]Sriram Venkateshan, Alap Patel, Kuruvilla Varghese:
Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2221-2232 (2015)
Conference and Workshop Papers
- 2023
- [c24]Shrutheesh Raman Iyer, Kuruvilla Varghese, Raghu Krishnapuram, Panini Bhamidipati:
Deep-Feature-Based Visual Odometry for Autonomous Emergency Parking. AIR 2023: 61:1-61:6 - [c23]Ajay S, Praveen V. S, Kuruvilla Varghese:
An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment. APCCAS 2023: 40-44 - [c22]A. BhanuPrasad, Kuruvilla Varghese:
High Throughput Hardware Acceleration for Image Generation using HLS. APCCAS 2023: 309-313 - [c21]Sadhu Sai Ram, Kuruvilla Varghese:
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. APCCAS 2023: 343-347 - [c20]Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese:
Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core. VLSID 2023: 42-47 - 2022
- [c19]Ramakant Joshi, Kuruvilla Varghese:
High-Level Synthesis of Geant4 Particle Transport Application for FPGA. DSD 2022: 75-83 - [c18]Dola Ram, Suraj Panwar, Kuruvilla Varghese:
Hardware Accelerator for Capsule Network based Reinforcement Learning. VLSID 2022: 162-167 - [c17]V. Naveen Chander, Kuruvilla Varghese:
A Soft RISC-V Vector Processor for Edge-AI. VLSID 2022: 263-268 - 2021
- [c16]Srikrishna Acharya, S. Sadgun S. Devanahalli, Alok Rawat, Kuruvilla Varghese, Pratik Sharma, Bharadwaj Amrutur, Ashish Joglekar, Raghu Krishnapuram, Yogesh Simmhan, Himanshu Tyagi:
Network Emulation For Tele-driving Application Development. COMSNETS 2021: 109-110 - 2020
- [c15]T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese:
Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. DSD 2020: 340-343 - [c14]Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur:
A RISC-V ISA Compatible Processor IP. VDAT 2020: 1-6 - 2018
- [c13]Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese:
FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training. DSD 2018: 381-388 - 2017
- [c12]Arnab Dey, Sebin Jose, Kuruvilla Varghese, Shayan Garani Srinivasa:
A high-throughput clock-less architecture for soft-output Viterbi detection. MWSCAS 2017: 779-782 - [c11]Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur:
A Custom Designed RISC-V ISA Compatible Processor for SoC. VDAT 2017: 570-577 - 2016
- [c10]Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa:
A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. VLSID 2016: 439-444 - 2013
- [c9]Karthikeyan Pandiyarajan, Srijith Haridas, Kuruvilla Varghese:
Transparent FPGA based device for SQL DDoS mitigation. FPT 2013: 82-89 - 2012
- [c8]Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese:
HD Resolution Intra Prediction Architecture for H.264 Decoder. VLSI Design 2012: 107-112 - 2011
- [c7]Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese:
A scalable network port scan detection system on FPGA. FPT 2011: 1-6 - 2010
- [c6]Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese:
Area optimized H.264 Intra prediction architecture for 1080p HD resolution. ASAP 2010: 297-300 - [c5]Gandhi Arpit, Raghavendra Adiga, Kuruvilla Varghese:
Space Efficient Diagonal Linear Space Sequence Alignment. BIBE 2010: 244-249 - [c4]Vrishali Vijay Nimbalkar, Kuruvilla Varghese:
In-channel Flow Control Scheme for Network-on-Chip. DSD 2010: 459-466 - 2009
- [c3]G. Vikas, Joy Kuri, Kuruvilla Varghese:
Power optimal Network-on-Chip interconnect design. SoCC 2009: 147-150 - 2008
- [c2]J. Divyasree, H. Rajashekar, Kuruvilla Varghese:
Dynamically reconfigurable regular expression matching architecture. ASAP 2008: 120-125 - [c1]Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese:
A Scalable High Throughput Firewall in FPGA. FCCM 2008: 43-52
Coauthor Index
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