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ORCIDNobuaki Otsuka
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2010 – 2019
- 2010
[j3]Kenichi Agawa, Shin-ichiro Ishizuka, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Asuka Maki, Go Urakawa, Tadashi Terada, Nobuyuki Itoh, Mototsugu Hamada, Fumie Fujii, Tadamasa Kato, Sadayuki Yoshitomi, Nobuaki Otsuka:
A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation. IEICE Trans. Electron. 93-C(6): 803-811 (2010)
2000 – 2009
- 2008
- [c7]Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka:
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. ISSCC 2008: 276-277 - [c6]Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Akihito Tohata, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka:
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell. ISSCC 2008: 382-383 - [c5]Tamio Ikehashi, Takayuki Miyazaki, Hiroaki Yamazaki, Atsushi Suzuki, Etsuji Ogawa, Shinji Miyano, Tomohiro Saito, Tatsuya Ohguro, Takeshi Miyagi, Yoshiaki Sugizaki, Nobuaki Otsuka, Hideki Shibata, Yoshiaki Toyoshima:
An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation. ISSCC 2008: 582-583 - [c4]Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka:
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation. ITC 2008: 1-7 - 2007
- [c3]Kenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shin-ichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa, Nobuyuki Itoh, Mototsugu Hamada, Nobuaki Otsuka:
A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range. CICC 2007: 655-658 - 2006
- [j2]Yasuhisa Takeyama, Hiroyuki Otake, Osamu Hirabayashi, Keiichi Kushida, Nobuaki Otsuka:
A low leakage SRAM macro with replica cell biasing scheme. IEEE J. Solid State Circuits 41(4): 815-822 (2006) - 2005
- [c2]Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama:
DFT techniques for memory macro with built-in ECC. MTDT 2005: 109-114 - 2002
- [c1]Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka:
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ITC 2002: 164-169
1990 – 1999
- 1997
- [j1]Nobuaki Otsuka, Mark A. Horowitz:
Circuit techniques for 1.5-V power supply flash memory. IEEE J. Solid State Circuits 32(8): 1217-1230 (1997)
Coauthor Index
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