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ORCIDPawel Chodowiec
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2000 – 2009
- 2009
[p1]Kris Gaj, Pawel Chodowiec:
FPGA and ASIC Implementations of AES. Cryptographic Engineering 2009: 235-294- 2005
- [j1]Viktor Fischer, Milos Drutarovský
, Pawel Chodowiec, F. Gramain:
InvMixColumn decomposition and multilevel resource sharing in AES implementations. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 989-992 (2005) - 2003
- [c6]Pawel Chodowiec, Kris Gaj:
Very Compact FPGA Implementation of the AES Algorithm. CHES 2003: 319-333 - [c5]Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj:
IPsec-Protected Transport of HDTV over IP. FPL 2003: 869-879 - 2001
- [c4]Kris Gaj, Pawel Chodowiec:
Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays. CT-RSA 2001: 84-99 - [c3]Pawel Chodowiec, Po Khuon, Kris Gaj:
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. FPGA 2001: 94-102 - [c2]Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott:
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. ISC 2001: 220-234 - 2000
- [c1]Kris Gaj, Pawel Chodowiec:
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. AES Candidate Conference 2000: 40-54
Coauthor Index
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