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ORCIDRainer G. Spallek
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- affiliation: Dresden University of Technology, Germany
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2020 – today
- 2020
[c58]Mohammed Bawatna
, Oliver Knodel, Rainer G. Spallek:
Real-Time Data Compression System for Data-Intensive Scientific Applications Using FPGA Architecture. CSOC (3) 2020: 304-313- [c57]Mohammed Bawatna, Oliver Knodel, Rainer G. Spallek:
Possibilities and Challenges for Reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific Applications. SDS 2020: 37-42
2010 – 2019
- 2019
- [c56]Mohammed Bawatna, Bertram Green, Sergey Kovalev, Jan-Christoph Deinert, Oliver Knodel, Rainer G. Spallek:
Research and implementation of efficient parallel processing of big data at TELBE user facility. SummerSim 2019: 56:1-56:6 - [c55]Mohammed Bawatna, Bertram Green, Sergey Kovalev, Jan-Christoph Deinert, Oliver Knodel, Rainer G. Spallek:
Research and Implementation of Efficient Parallel Processing of Big Data at TELBE User Facility. SPECTS 2019: 1-6 - 2017
- [c54]Oliver Knodel, Steffen Köhler, Marko Rößler, Rainer G. Spallek:
First Workshop on Hardware Defined Programming - HDP. GI-Jahrestagung 2017: 467-468 - [c53]Steffen Köhler, Rainer G. Spallek:
Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. GI-Jahrestagung 2017: 493-501 - [c52]Paul R. Genßler, Oliver Knodel, Rainer G. Spallek:
A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture. GI-Jahrestagung 2017: 531-542 - 2016
- [j1]Oliver Knodel, Paul R. Genssler, Rainer G. Spallek:
Migration of long-running Tasks between Reconfigurable Resources using Virtualization. SIGARCH Comput. Archit. News 44(4): 56-61 (2016) - [c51]Oliver Knodel, Patrick Lehmann, Rainer G. Spallek:
RC3E: Reconfigurable Accelerators in Data Centres and Their Provision by Adapted Service Models. CLOUD 2016: 19-26 - [c50]Thomas B. Preußer, Martin Zabel, Patrick Lehmann, Rainer G. Spallek:
The portable open-source IP core and utility library PoC. ReConFig 2016: 1-6 - 2015
- [c49]Oliver Knodel, Rainer G. Spallek:
Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud. DSD 2015: 337-344 - [c48]Kai-Uwe Irrgang, Thomas B. Preußer, Rainer G. Spallek:
Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. GI-Jahrestagung 2015: 1385-1398 - [i1]Oliver Knodel, Rainer G. Spallek:
RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment. CoRR abs/1508.06843 (2015) - 2014
- [c47]Oliver Knodel, Martin Zabel, Patrick Lehmann, Rainer G. Spallek:
Educating hardware design - From primary school children to postgraduate engineers. FPL 2014: 1-4 - [c46]Thomas B. Preußer, Rainer G. Spallek:
Ready PCIe data streaming solutions for FPGAs. FPL 2014: 1-4 - [c45]Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek:
PoC-align: An open-source alignment accelerator using FPGAs. ReConFig 2014: 1-6 - 2013
- [c44]Oliver Knodel, Rainer G. Spallek:
Integration of a multi-FPGA system in a common cluster environment. FPL 2013: 1-2 - [c43]Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, Rainer G. Spallek:
Weasel: A platform-independent streaming-optimized SATA controller. FPL 2013: 1-4 - [c42]Oliver Knodel, Andy Georgi, Patrick Lehmann, Wolfgang E. Nagel, Rainer G. Spallek:
Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures. ICPP 2013: 893-900 - [c41]Marco Kaufmann, Rainer G. Spallek:
Superblock compilation and other optimization techniques for a Java-based DPT machine emulator. VEE 2013: 33-40 - 2012
- [c40]Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek:
Short-Read Mapping by a Systolic Custom FPGA Computation. FCCM 2012: 169-176 - [c39]Kai-Uwe Irrgang, Rainer G. Spallek:
Comparison of Trace-Port-Designs for On-Chip-Instruction-Trace. IEEE GSC 2012 - [c38]Martin Zabel, Thomas B. Preußer, Rainer G. Spallek:
Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. JTRES 2012: 88-97 - 2011
- [c37]Thomas B. Preußer, Martin Zabel, Rainer G. Spallek:
Accelerating Computations on FPGA Carry Chains by Operand Compaction. IEEE Symposium on Computer Arithmetic 2011: 95-102 - [c36]Oliver Knodel, Thomas B. Preußer, Rainer G. Spallek:
Next-generation massively parallel short-read mapping on FPGAs. ASAP 2011: 195-201 - [c35]Marco Kaufmann, Matthias Häsing, Thomas Preußer, Rainer G. Spallek:
The Java Virtual Machine in retargetable, high-performance instruction set simulation. PPPJ 2011: 21-30 - 2010
- [c34]Thomas B. Preußer, Peter Reichel, Rainer G. Spallek:
An Embedded GC Module with Support for Multiple Mutators and Weak References. ARCS 2010: 25-36 - [c33]Thomas B. Preußer, Rainer G. Spallek:
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. FPL 2010: 318-325 - [c32]Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek:
Solving Sudokus through an incidence matrix on an FPGA. FPT 2010: 465-469 - [c31]Martin Zabel, Rainer G. Spallek:
Application requirements and efficiency of embedded Java bytecode multi-cores. JTRES 2010: 46-52
2000 – 2009
- 2009
- [c30]Jens Braunes, Rainer G. Spallek:
Generating the trace qualification configuration for MCDS from a high level language. DATE 2009: 1560-1563 - [c29]Thomas B. Preußer, Rainer G. Spallek:
Mapping basic prefix computations to fast carry-chain structures. FPL 2009: 604-608 - [c28]Martin Zabel, Thomas B. Preußer, Rainer G. Spallek:
High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. MBMV 2009: 187-196 - 2008
- [c27]Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek:
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ARC 2008: 296-301 - [c26]Thomas Preußer, Rainer G. Spallek:
Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. ESA 2008: 260-264 - [e1]Uwe Brinkschulte, Theo Ungerer, Christian Hochberger, Rainer G. Spallek:
Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings. Lecture Notes in Computer Science 4934, Springer 2008, ISBN 978-3-540-78152-3 [contents] - 2007
- [c25]Jörg Schneider, Marcel Naggatz, Rainer G. Spallek:
Implementation of Architecture Concepts for Hardware Agent Systems. CIT 2007: 823-828 - [c24]Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek:
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. DSD 2007: 59-62 - [c23]Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Enabling constant-time interface method dispatch in embedded Java processors. JTRES 2007: 196-205 - [c22]Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Bump-pointer method caching for embedded Java processors. JTRES 2007: 206-210 - 2006
- [c21]Jens Braunes, Rainer G. Spallek:
A Compiler-Oriented Architecture Description for Reconfigurable Systems. ARC 2006: 443-448 - [c20]Steffen Köhler, Martin Zimmerling, Martin Zabel, Rainer G. Spallek:
Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. ARCS Workshops 2006: 142-151 - [c19]Thomas B. Preußer, Rainer G. Spallek:
Analysis of a Fully-Scalable Digital Fractional Clock Divider. ASAP 2006: 173-177 - 2005
- [c18]Jens Braunes, Steffen Köhler, Annett Königsmann, Rainer G. Spallek:
Ein Zwischenformat-Profiler für das RECAST-Framework. ARCS Workshops 2005: 33-38 - [c17]Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek:
Design space exploration of coarse-grain reconfigurable DSPs. ReConFig 2005 - 2004
- [c16]Jens Braunes, Steffen Köhler, Rainer G. Spallek:
RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ARCS 2004: 156-166 - [c15]Thomas Preußer, Steffen Köhler, Rainer G. Spallek:
RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. ESA/VLSI 2004: 130-135 - [c14]Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. FPL 2004: 781-790 - 2003
- [c13]Sergej Sawitzki, Rainer G. Spallek:
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. FPL 2003: 1119-1122 - 2002
- [c12]Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz:
A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. FPL 2002: 1164-1167 - [c11]Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek:
Improving Code Efficiency for Reconfigurable VLIW Processors. IPDPS 2002 - 2001
- [c10]Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek:
Prototyping Framework for Reconfigurable Processors. FPL 2001: 6-16 - 2000
- [c9]Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube:
Formal Verification for Microprocessors with Extendable Instruction Set. ASAP 2000: 47-55 - [c8]Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube:
Formal Verification of a Reconfigurable Microprocessor. FPL 2000: 781-784 - [c7]Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek, Jörg Schneider, S. Rülke:
Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. MBMV 2000: 236-244
1990 – 1999
- 1999
- [c6]Sergej Sawitzki, Rainer G. Spallek:
A Concept for an Evaluation Framework for Reconfigurable Systems. FPL 1999: 475-480 - [c5]Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek:
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. IPPS/SPDP Workshops 1999: 706-708 - 1998
- [c4]Sergej Sawitzki, Achim Gratz, Rainer G. Spallek:
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. FPL 1998: 411-415 - [c3]Raimar Falke, Michael Peter, Achim Gratz, Rainer G. Spallek:
Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen. Java-Informations-Tage 1998: 354-363 - 1997
- [c2]Gert Markwardt, Günter Kemnitz, Rainer G. Spallek:
A RISC Processor with Extended Forwarding. ARCS 1997: 163-169 - [c1]Achim Gratz, Rainer G. Spallek:
Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen. MMB (Kurzbeiträge) 1997: 51-58
Coauthor Index
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