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2000 – 2009
- 2002
[j5]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu
, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Methodology for Systems on Chip. IEEE Micro 22(5): 69-81 (2002)- [c5]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs. DATE 2002: 486-490
1990 – 1999
- 1993
- [j4]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 410-424 (1993) - 1991
- [j3]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 994-1005 (1991) - [j2]Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin:
Channel density reduction by routing over the cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1067-1071 (1991) - [c4]Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin:
Channel Density Reduction by Routing Over The Cells. DAC 1991: 120-125 - [c3]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486 - 1990
- [j1]Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 781-786 (1990) - [c2]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: A Cell Layout Generator. DAC 1990: 474-479
1980 – 1989
- 1989
- [c1]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD 1989: 344-347
Coauthor Index
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