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ORCID31st RSP 2020: Hamburg, Germany
- International Workshop on Rapid System Prototyping, RSP 2020, Hamburg, Germany, September 24-25, 2020. IEEE 2020, ISBN 978-1-7281-8466-1
- Daniel Gis, Nils Büscher, Christian Haubelt:
Advanced Debugging Architecture for Smart Inertial Sensors using Sensor-in-the-Loop. 1-7 - Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot:
(System)Verilog to Chisel Translation for Faster Hardware Design. 1-7 - Jérémy Nadal, Amer Baghdadi:
FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding. 1-7 - Chen Wu, Virginie Fresse, Benoît Suffran
, Hubert Konik:
Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing cluster. 1-7 - José D. Domingues, Fábio D. L. Coutinho, Pedro M. C. Marques, Samuel Santos Pereira, Hugerles S. Silva, Arnaldo S. R. Oliveira:
MPSoC Fast Prototyping of a Reconfigurable DU Downlink Transmission Chain for 5G New Radio. 1-7 - Xuzhi Zhang, Narendra Prabhu, Russell Tessier:
NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks. 1-7 - Erwan Lenormand, Thierry Goubier, Loïc Cudennec, Henri-Pierre Charles:
A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management. 1-7 - Seyed Alireza Damghani, Jean-Philippe Legault, Kenneth B. Kent:
Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin II. 1-7 - Erwan Moréac, El Mehdi Abdali, François Berry, Dominique Heller, Jean-Philippe Diguet:
Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV. 1-7
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