![](https://dblp.uni-trier.de./img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de./img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de./img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
MEMSYS 2022: Washington, DC, USA
- Bruce L. Jacob:
Proceedings of the 2022 International Symposium on Memory Systems, MEMSYS 2022, Washington, DC, USA, October 3-6, 2022. ACM 2022, ISBN 978-1-4503-9800-8 - Kazi Asifuzzaman
, Mohammad Alaul Haque Monil
, Frank Liu, Jeffrey S. Vetter:
Evaluating HPC Kernels for Processing in Memory. 1:1-1:6 - Muhammad M. Rafique, Zhichun Zhu:
Dynamic Page Policy Using Perceptron Learning. 2:1-2:11 - Kaustav M. Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee:
A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices. 3:1-3:16 - Gunnar Carlstedt
, Mats Rimborg
:
Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore Processor. 4:1-4:12 - Sayed Ahmad Salehi:
In-memory Bulk Bitwise Logic Operation for Multi-level Cell Non-volatile Memories. 5:1-5:5 - Lukas Steiner
, Chirag Sudarshan
, Matthias Jung
, Dominik Stoffel
, Norbert Wehn
:
A Framework for Formal Verification of DRAM Controllers. 6:1-6:7 - Samiksha Verma, Shirshendu Das, Vipul Bondre:
Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly. 7:1-7:11 - Hüsrev Cilasun
, Chris Macaraeg, Ivy Bo Peng
, Abhik Sarkar, Maya B. Gokhale
:
FPGA-accelerated simulation of variable latency memory systems. 8:1-8:11 - Lukas Steiner
, Matthias Jung
, Michael Huonker, Norbert Wehn
:
Unveiling the Real Performance of LPDDR5 Memories. 9:1-9:3 - Thaleia Dimitra Doudali
, Ada Gavrilovska
:
Cronus: Computer Vision-based Machine Intelligent Hybrid Memory Management. 10:1-10:11 - Amit Berman
:
Exploiting Data Source Distribution to Enhance NVM Reliability. 11:1-11:7 - Jennie Hill, Justin A. Blanco, James Shey, Ryan N. Rakvic, T. Owens Walker III:
Toward Classification of Phase Change Memory and 3D NAND Flash SSDs Using Power-based Side-channel Analysis in the Time-domain. 12:1-12:7
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.