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MEDEA@PACT 2004: Antibes Juan-les-Pins, France

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Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004. ACM 2004
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Guests editor's introduction. 1-2
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Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin:
Energy aware memory architecture configuration. 3-9
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Hyo-Joong Suh, Sung Woo Chung:
DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency. 10-16
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Sami Yehia, Jean-Francois Collard, Olivier Temam:
Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios. 17-24
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Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa:
Locality analysis to control dynamically way-adaptable caches. 25-32
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Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori:
SH-X: an embedded processor core for consumer appliances. 33-40
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Afrin Naz, Mehran Rezaei, Krishna Kavi, Philip H. Sweany:
Improving data cache performance with integrated use of split caches, victim cache and stream buffers. 41-48
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Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency. 49-56
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Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications. 57-62

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