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ORCID2nd ASYNC 1996: Aizu-Wakamatsu, Fukushima, Japan
- 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan. IEEE Computer Society 1996, ISBN 0-8186-7298-6
Session 1: High-Speed Design
- Per Torstein Røine:
A system for asynchronous high-speed chip to chip communication. 2-10 - Stephen B. Furber, Jianwei Liu:
Dynamic logic in four-phase micropipelines. 11-16 - Kenneth Y. Yun, Peter A. Beerel, Julio Arceo:
High-performance asynchronous pipeline circuits. 17-28
Session 2: Logic Synthesis
- Toshiyuki Miyamoto, Sadatoshi Kumagai:
An efficient algorithm for deriving logic functions of asynchronous circuits. 30-35 - Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Yakovlev:
Complete state encoding based on the theory of regions. 36-47 - Steven M. Burns:
General conditions for the decomposition of state holding elements. 48-57
Session 3: Architectural Synthesis
- William F. Richardson, Erik Brunvand:
Fred: an architecture for a self-timed decoupled computer. 60-68 - Tony Werner, Venkatesh Akella:
Counterflow pipeline based dynamic instruction scheduling. 69-79 - D. K. Arvind, Vinod E. F. Rebello:
Static scheduling of instructions on micronet-based asynchronous processors. 80-91
Session 4: Formal Methods
- Nozar Tabrizi, Michael J. Liebelt
, Kamran Eshraghian:
Dynamic hazards and speed independent delay model. 94-103 - Martin E. Bush, Mark B. Josephs:
Some limitations to speed-independence in asynchronous circuits. 104-111 - Paul G. Lucassen, Jan Tijmen Udding:
On the correctness of the Sproull counterflow pipeline processor. 112-120
Session 5: Novel Techniques
- Kees van Berkel, Arjan Bink:
Single-track handshake signaling with application to micropipelines and handshake circuits. 122-133 - Masaaki Maezawa, Itaru Kurosawa, Yoshio Kameda, Takashi Nanya:
Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits. 134-142 - Eckhard Grass, Richard C. S. Morling, Izzet Kale:
Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing. 143-149
Session 6: Design Automation and Measurements
- Tomohiro Yoneda, Takashi Yoshikawa:
Using partial orders for trace theoretic verification of asynchronous circuits. 152-163 - Rakefet Kol, Ran Ginosar, Goel Samuel:
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. 164-174 - Clark Foley:
Characterizing metastability. 175-184
Session 7: Low Power and System Design
- José A. Tierno, Rajit Manohar, Alain J. Martin:
The energy and entropy of VLSI computations. 188-196 - Lars Skovby Nielsen, Jens Sparsø:
A low-power asynchronous data-path for a FIR filter bank. 197-207 - Jim D. Garside, Steve Temple, Rahul Mehra:
The AMULET2e cache system. 208-217
Session 8: Logic Optimization
- Marco A. Peña, Jordi Cortadella:
Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits. 222-232 - Tilman Kolks, Steven Vercauteren, Bill Lin:
Control resynthesis for control-dominated asynchronous designs. 233-243 - Peter A. Beerel, Kenneth Y. Yun, Wei-Chun Chou:
Optimizing average-case delay in technology mapping of burst-mode circuits. 244-260
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