default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID5th GPGPU@ASPLOS 2012: London, UK
- David R. Kaeli, John Cavazos, Enqiang Sun:
The 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, GPGPU-5, London, United Kingdom, March 3, 2012. ACM 2012, ISBN 978-1-4503-1233-2 - Cedric Nugteren, Henk Corporaal:
Introducing 'Bones': a parallelizing source-to-source compiler based on algorithmic skeletons. 1-10 - Jeremy S. Meredith, Robert Sisneros, David Pugmire, Sean Ahern:
A distributed data-parallel framework for analysis and visualization algorithm development. 11-19 - Takefumi Miyoshi, Hidetsugu Irie, Keigo Shima, Hiroki Honda, Masaaki Kondo, Tsutomu Yoshinaga:
FLAT: a GPU programming framework to provide embedded MPI. 20-29 - Feiwen Zhu, Peng Chen, Donglei Yang, Weihua Zhang, Haibo Chen, Binyu Zang:
A GPU-based high-throughput image retrieval algorithm. 30-37 - Mark Kim
, Guoning Chen, Charles D. Hansen:
Dynamic particle system for mesh extraction on the GPU. 38-46 - Jeswin Godwin, Justin Holewinski, P. Sadayappan:
High-performance sparse matrix-vector multiplication on GPUs for structured grid computations. 47-56 - Akira Nukada, Yutaka Maruyama, Satoshi Matsuoka:
High performance 3-D FFT using multiple CUDA GPUs. 57-63 - Mehrzad Samadi, Amir Hormati, Janghaeng Lee, Scott A. Mahlke:
Paragon: collaborative speculative loop execution on GPU and CPU. 64-73 - Wojciech Zaremba, Yuan Lin, Vinod Grover:
JaBEE: framework for object-oriented Java bytecode compilation and execution on graphics processor units. 74-83 - Enqiang Sun, Dana Schaa, Richard Bagley, Norman Rubin, David R. Kaeli:
Enabling task-level scheduling on heterogeneous platforms. 84-93 - Per Ganestam, Michael C. Doggett:
Auto-tuning interactive ray tracing using an analytical GPU architecture model. 94-100 - Shivani Raghav, Andrea Marongiu, Christian Pinto, David Atienza, Martino Ruggiero, Luca Benini:
Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting. 101-109 - Hyojin Choi, Jae-Woo Ahn, Wonyong Sung:
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs. 110-119
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-21 19:39 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
