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ORCID5th IEEE Symposium on Computer Arithmetic 1981: Ann Arbor, MI, USA
- Kishor S. Trivedi, Daniel E. Atkins:
5th IEEE Symposium on Computer Arithmetic, ARITH 1981, Ann Arbor, MI, USA, May 16-19, 1981. IEEE Computer Society 1981 - T. R. N. Rao:
Arithmetic of finite fields. 1-5 - Panos A. Ligomenides, Robert Newcomb:
Complement representations in the Fibonacci computer. 6-9 - T. Mahadeva Rao, Robert T. Gregory:
The conversion of Hensel codes to rational numbers. 10-20 - Shauchi Ong, Daniel E. Atkins:
Towards quantitative comparison of computer number systems. 21-33 - James E. Robertson:
A systematic approach to the design of structures for arithmetic. 35-41 - Diem Dinh Nguyen:
A systematic approach to the design of structures for addition and subtraction - Case of radix r = mk. 42-49 - J. B. Gosling, John H. Zurawski, David B. G. Edwards:
A chip-set for a high-speed low-cost floating-point unit. 50-55 - Robert Michael Owens:
Compound algorithms for digit online arithmetic. 64-71 - Abdolali Gorji-Sinaki, Milos D. Ercegovac:
Design of a digit-slice on-line arithmetic unit. 72-80 - Osaaki Watanuki, Milos D. Ercegovac:
Floating-point on-line arithmetic: Algorithms. 81-86 - Osaaki Watanuki, Milos D. Ercegovac:
Floating-point on-line arithmetic: Error analysis. 87-91 - Cauligi S. Raghavendra, Milos D. Ercegovac:
A simulator for on-line arithmetic. 92-98 - Hong Peng:
Algorithms for extracting square roots and cube roots. 121-126 - George S. Taylor:
Compatible hardware for division and square root. 127-134 - Robert Willoner, I-Ngo Chen:
An algorithm for modular exponentiation. 135-138 - P. Michael Farmwald:
High bandwidth evaluation of elementary functions. 139-142 - Robert T. Gregory:
Residue arithmetic with rational operands. 144-145 - Saroj Kaushik, R. K. Arora:
Sign detection in the Symmetric Residue Number System. 146-151 - Gregory Walker:
Extension of the MC68000 architecture to include Standard Floating-point arithmetic. 179-183 - Rob A. Rutenbar
, Y. E. Park:
Case study of a VLSI design project: A simple inner product machine. 184-189 - George S. Taylor, David A. Patterson:
VAX hardware for the proposed IEEE floating-point standard. 190-196 - Kai Hwang, Yeng-Heng Cheng:
Partitioned algorithms and VLSI structures for large-scale matrix computations. 222-232 - Peter Kornerup, David W. Matula:
An integrated rational arithmetic unit. 233-240 - Mary Jane Irwin, Dwight R. Smith:
A rational arithmetic processor. 241-244 - Hideaki Kobayashi:
A fast multi-operand multiplication scheme. 246-250 - Christos A. Papachristou:
Algorithms for parallel addition and parallel polynomial evaluation. 256-263 - Svetoslav Markov:
On an interval arithmetic and its applications. 274-277
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