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ORCIDANCS 2007: Orlando, Florida, USA
- Raj Yavatkar, Dirk Grunwald, K. K. Ramakrishnan:
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2007, Orlando, Florida, USA, December 3-4, 2007. ACM 2007, ISBN 978-1-59593-945-6
Architecture
- Tomás Hrubý, Kees van Reeuwijk, Herbert Bos
:
Ruler: high-speed packet matching and rewriting on NPUs. 1-10 - Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang:
Optimization of pattern matching algorithm for memory based architecture. 11-16 - Yaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu, Jun Li:
Towards high-performance flow-level packet processing on multi-core network processors. 17-26 - John Giacomoni, John K. Bennett, Antonio Carzaniga, Douglas C. Sicker, Manish Vachharajani, Alexander L. Wolf:
Frame shared memory: line-rate networking on commodity hardware. 27-36
Poster session
- Charlie Wiseman, Jonathan S. Turner, Ken Wong, Brandon Heller:
Experimental evaluation of a coarse-grained switch scheduler. 37-38 - Tilman Wolf:
Design of a network architecture with inherent data path security. 39-40 - Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McKeown:
Experimenting with buffer sizes in routers. 41-42 - Randy Smith, Dan Gibson, Shijin Kong:
To CMP or not to CMP: analyzing packet classification on modern and traditional parallel architectures. 43-44 - Lei Shi, Bin Liu, Changhua Sun, Zhengyu Yin, Laxmi N. Bhuyan, H. Jonathan Chao:
Flow-slice: a novel load-balancing scheme for multi-path switching systems. 45-46
Hardware
- Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. 47-56 - Bryan Veal, Annie P. Foong:
Performance scalability of a multi-core web server. 57-66 - Arindam Mallik, Yu Zhang, Gokhan Memik:
Automated task distribution in multicore network processors using statistical analysis. 67-76 - Lin Liu, Yuanyuan Yang:
Optimal packet scheduling in output-buffered optical switches with limited-range wavelength conversion. 77-86
Switch optimization
- Wladek Olesinski, Nils Gura, Hans Eberle, Andres Mejia:
Low-latency scheduling in large switches. 87-96 - Wickus Nienaber, Xin Yuan, Zhenhai Duan:
On LID assignment in infiniBand networks. 97-106 - Bill Lin, Isaac Keslassy:
Frame-aggregated concurrent matching switch. 107-116 - Nikolaos Chrysos:
Congestion management for non-blocking clos networks. 117-126
Regular expressions & pattern matching
- Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan:
Compiling PCRE to FPGA for accelerating SNORT IDS. 127-136 - Hyesook Lim, Ju Hyoung Mun:
High-speed packet classification using binary search on length. 137-144 - Michela Becchi, Patrick Crowley:
An improved algorithm to accelerate regular expression evaluation. 145-154 - Sailesh Kumar, Balakrishnan Chandrasekaran, Jonathan S. Turner, George Varghese:
Curing regular expressions matching algorithms from insomnia, amnesia, and acalculia. 155-164
Detection and inspection
- Michele Colajanni, Daniele Gozzi, Mirco Marchetti:
Enhancing interoperability and stateful analysis of cooperative network intrusion detection systems. 165-174 - Sheng-Ya Lin, Cheng-Chung Tan, Jyh-Charn Liu, Michael Oehler:
High-speed detection of unsolicited bulk emails. 175-184 - Arup Acharya, Xiping Wang, Charles Wright:
A programmable message classification engine for session initiation protocol (SIP). 185-194 - Christopher L. Hayes, Yan Luo:
DPICO: a high speed deep packet inspection engine using compact finite automata. 195-203
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