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ORCID9. IEEE INTERACT 2005: San Francisco, California, USA
- 9th Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT-9 2005, San Francisco, California, USA, February 13, 2005. IEEE Computer Society 2005, ISBN 0-7695-2321-8
Compiling for CMP
- Carlos Molina, Antonio González
, Jordi Tubella:
Compiler analysis for trace-level speculative multithreaded architectures. 2-10 - Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara:
Multigrain parallel processing on compiler cooperative chip multiprocessor. 11-20
Compiling for Itanium Architecture
- Markus Mock, Ricardo Villamarín-Salomón, José Baiocchi:
An empirical study of data speculation use on the Intel Itanium 2 processor. 22-33 - Alex Shye, Matthew Iyer, Tipp Moseley, David Hodgdon, Dan Fay, Vijay Janapa Reddi, Daniel A. Connors:
Analysis of path profiling information generated with performance monitoring hardware. 34-43
Data Cache Optimization Techniques
- Jennifer B. Sartor, Subramaniam Venkiteswaran, Kathryn S. McKinley, Zhenlin Wang:
Cooperative caching with keep-me and evict-me. 46-57 - Mohamed M. Zahran, Anasua Bhowmik:
Hybrid compiler and microarchitecture technique for cache traffic optimization. 58-69 - Evangelia Athanasaki, Nectarios Koziris, Panayotis Tsanakas:
A tile size selection analysis for blocked array layouts. 70-80
Instrumentations and Compiler Optimizations
- Simon Kågström, Håkan Grahn, Lars Lundberg:
Automatic low overhead program instrumentation with the LOPI framework. 82-93 - Kaiyu Chen, Sun Chan, Roy Dz-Ching Ju, Peng Tu:
Optimizing structures in object oriented programs. 94-103
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